This invention relates generally to the field of chip design and more particularly to placement for bit slice circuitry.
Semiconductor chips are vastly complex arrangements of circuitry, being composed of numerous smaller components. With each successive generation of semiconductor chips, more and more components are incorporated onto a single chip. These components can take the form of hard macros, soft macros, and individual cells or gates. Hard macros are structures with pre-defined, inflexible shapes with on-chip memories being a typical example. Soft macros contain a combination of components, often including smaller hard macros, smaller soft macros, and cells. The components inside a soft macro can be shifted around to optimize the layout of the chip. The cells or gates form the smallest units that provide logical function with examples being NOR gates and flip flops. These cells are fixed in shape but can be moved around as needed and even replicated or cloned to aid in the overall layout, timing, or any other chip parameter that needs to be optimized. These cells can, in turn, be placed in locations that appear to be rather random. The random placement results in the interconnect wiring appearing to be a “rat's nest” on the metallization layers of a chip.
There are certain, well understood soft macro types which do not behave well when composed of rather randomly placed cells with the corresponding rather random interconnect wiring. Examples of these types of macros for which randomness is detrimental include multipliers and register files.
Regularity is beneficial on these types of soft macros. A multiplier is often composed of numerous full-adder cells. By placing the full-adder cells in a very specific, regular arrangement the interconnection between the cells is also very regular. By having regular placement and the resulting regular wiring, timing is predictable and consistent between the various stages. Oftentimes there are pipeline stages where progressive calculations are performed and intermediate results stored. By maintaining regular placement of the pipeline stages, again the interconnect wiring, timing, and other key aspects of the chip design are regular, predictable, and highly optimized.
This type of regular placing of cells is often referred to as structured placement. Historically, structured placement has been manually performed to hand optimize the layout arrangement of the cells. Hand placement has been the only way to avoid the apparently random placement and irregular interconnect that is quite problematical for certain macros. Just identifying which cells need to be regularly placed is itself a perplexing problem. Once identified, correct regular placement of the needed cells via automation is still difficult.
Often, in the midst of this circuitry there are regular, repeated logic structures referred to as bit slices. These bit slices are an arrangement of logic cells. An example of a bit slice may be a group of flip flops that form an address in a register file. Another example of a bit slice may be a group of cells that form a portion of an arithmetic logic unit (ALU). A third example of a bit slice may be a row of full adders that form part of a multiplier unit. Any group of cells which are identical and repeated may be considered a bit slice. Further a group of similar cells which are repeated may be considered a bit slice.
The problem is that a bit slice is regular structure and benefits from regular placement, yet automatically placing of bit slices has not resulted in a regular placement.